In 1992 the Joint Electron Device Engineering Council (JEDEC) of the Electronic Industries Association (EIA) passed a new low voltage integrated circuit standard based on a 3.3 v nominal power supply. This new low voltage standard is designated the JEDEC Standard 8-1A and is now commonly known as the 3 v standard. The new JEDEC Standard 8-1A at nominal 3.3 v is incompatible with the conventional integrated circuit JEDEC Standards 18 and 20 specifying a 5 v power supply.
In NWELL CMOS technology, the P channel or PMOS transistors are formed with P source and drain regions formed in an NWELL which is in turn formed in a grounded P type substrate. The NWELL of a PMOS output pullup transistor of the output buffer circuit is coupled to the high potential power rail VCC. If a standard output buffer circuit supplied by the new 3.3 v standard power supply has a 5 v signal applied to its output from the common external bus, the PN junction between the P drain and NWELL will forward bias. This creates a low impedance path from the 5 v common external bus, to the internal 3.3 v power rail with disruptive effects. It is therefore generally not allowed to have on a common external bus multiple tristate output buffer circuits with incompatible power supplies.
One solution to this problem is described in the related David H. Larsen and James B. Boomer U.S. patent application Ser. No. 08/016,009, filed Feb. 10, 1993 for FULL SWING POWER DOWN BUFFER CIRCUIT WITH MULTIPLE POWER SUPPLY ISOLATION. According to the Larsen and Boomer invention there is provided a P channel NWELL isolation switch transistor PW1 having a primary current path coupled between the NWELL of the pullup output transistor and the high potential power rail VCC. The NWELL isolation switch transistor PW1 has a control node coupled in the buffer circuit to the control node of the pullup output transistor for controlling the conducting state of the NWELL isolation switch transistor PW1 substantially in phase with the output pullup transistor. The NWELL of the pullup output transistor is thereby isolated from the high potential power rail VCC when the pullup output transistor is not conducting. The NWELL, isolation switch transistor PW1 avoids the leakage path from a 5 volt signal on the common output bus to the 3.3 v internal power supply rail of a quiet 3.3 v standard output buffer circuit on the common bus. As a result both 3.3 v and 5 v subsystems and output buffer circuits may coexist in the same common bus of a multiple output buffer circuit system.
Another solution is provided in the related Joseph D. Wert et al. U.S. patent application Ser. No. 08/073,376, filed
Jun. 7,1993 for OVERVOLTAGE PROTECTION BACKGATE BIAS SWITCHING CIRCUIT. According to the Wert et al. invention a 3.3 v/5 v backgate bias switching circuit or NWELL supply switching circuit is coupled between the output and the NWELL of the output buffer circuit output pullup transistor. Two P channel or PMOS transistors are coupled in series between the 3.3 v internal power supply rail and the output. The intermediate node between the two series coupled PMOS transistors is coupled to the NWELL of the output pullup transistor. A P channel passthrough gate transistor is also coupled between the intermediate node and the gate node of the output pullup transistor. By this arrangement, when the 3.3 v supply rail is applied at the gate node of the output pullup transistor, it is also applied at the NWELL. Similarly if a 5 v signal on the common bus finds its way to the gate node of the output pullup transistor, the 5 v signal is also applied to the NWELL. By this effective switching of the power supply applied to the NWELL of the output pullup transistor to match the signal at the drain node, a destructive leakage path between the 5 v common bus and 3.3 v internal power supply rail is avoided.